In the related art, when processing each frame, a potential at a pull-up node is pulled down to discharge after a gate driving signal is outputted from a current-level driving output node, so as to prevent a gate driving signal output control transistor from being turned on falsely during the processing of the current frame, thereby to prevent the occurrence of false output of the gate driving signal.
However, in the related art, generally the potential at the pull-up node is pulled down to discharge by using an output signal from a next-level shift register unit as a resetting signal. This output signal is a pulse signal with a very short duration, and limited electric quantity is released, so the pull-up node will be discharged incompletely.
Such an incomplete discharging for the intraframe processing might not be a big deal within a short period of time, but after the shift register unit operates for a long period of time, more electric quantity may be accumulated, resulting in that the pull-up node is at an inaccurate level. Furthermore, when the pull-up node is still maintained at a high level after the gate driving signal is outputted from the current-level driving output node, the gate driving signal output control transistor will be still in an on state, resulting in the false output of the gate driving signal.